Loading 載入中...
Holiday
EECS資電 208 M5M6RnR5
This course provides the fundamental knowledge of designing VLSI. It begins with a review of transistor theory and CMOS process technology. It then discusses the design, layout, simulation, and test considerations of a variety of CMOS logic circuits such as inverters, logic gates, flip-flops, and arithmetic circuits using different design st<x>yles (static logic, steering logic, or dynamic logic). Furthermore, system-level design, low-power techniques, semiconductor memories, and I/O plan will also be discussed in details.
MON | TUE | WED | THU | FRI | |
08:00108:50 | |||||
09:00209:50 | |||||
10:10311:00 | |||||
11:10412:00 | |||||
12:10n13:00 | |||||
13:20514:10 | |||||
14:20615:10 | |||||
15:30716:20 | |||||
16:30817:20 | |||||
17:30918:20 | |||||
18:30a19:20 | |||||
19:30b20:20 | |||||
20:30c21:20 |
平均百分制 86.82
標準差 7.72
平均百分制 76.16
標準差 12.12
平均百分制 83.19
標準差 12.22
本課程每週上課150分鐘,其餘時間由教授視情形彈性運用。
電機系3年級4年級,電資院學士班3年級4年級優先,第3次選課起開放全校修習
-